This task will add hardware model implementations for
riscv_32 cpu architecture within the next generation toolkit.
We will be working with the latest
uberspark.git, so make sure that your fork is up to date with the upstream
The following three references can be followed towards this task:
CPU hardware model documentation described in: uberspark/hwm.rst at develop · uberspark/uberspark · GitHub
x86_32hardware model task: überSpark: Add x86_32 hardware model to next-gen toolkit
armv8_32hardware model task: überSpark: Add armv7_32 and armv8_32 hardware model to next-gen toolkit
The CASM instructions that need to be implemented will be based on contents of assembly files within the following uobjcoll: uobjcoll-opensbi/firmware at uobjcoll · uberspark/uobjcoll-opensbi · GitHub
The CPU HWM will be housed in the following namespaces:
vexriscvis the target RISC-V cpu model. See: uberspark/hwm.rst at develop · uberspark/uberspark · GitHub
for more information on the CPU HWM namespace organization and how the existing
armmodels are organized along with their manifest contents.
When implementing the CASM instruction mnemonics and hardware model implementation please refer to Volume-1 and Volume-2 of the RISC-V ISA specification found here: Specifications - RISC-V International
The specs should give the the pseudo-code of what the instruction does. This pseudo-code will then be translated into the equivalent C implementation just like the
Working branches, PR and merge info follow: